Single Event Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled.

By: David F. Heidel, Kenneth P. Rodbell, Phil Oldiges, Michael S. Gordon, Henry Henry H. K. Tang, Ethan H. Cannon, Cristina Plettner

Published in: RC23891 in 2006


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