Development of Vacuum Underfill Technology for 3-D Chip Stack

We developed a vacuum underfill technology for 3-D chip stacks and for flip chips in high performance system integration. We fabricated a 3D prototype chip stack using the vacuum underfill technology to apply the adhesive. The underfill was injected into each 6-µm gaps in a 3-layer chip stack and no voids were detected in acoustic microscopy images. Electrical tests and thermal reliability tests were used to measure the resistance of the vertical interconnections and the impact of the underfill. The results showed there was minimal difference in the average interconnection resistance of the chip stack with and without underfill.

By: Katsuyuki Sakuma, Sayuri Kohara, Kuniaki Sueoka, Yasumitsu Orii, Mikio Kawakami, Kazuo Asai, Yoshikazu Hirayama, and John U. Knickerbocker

Published in: RT0926 in 2011


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Vacuum Underfill Technology_sakuma.pdf

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