Instruction-Set Synthesis for Reactive Real-Time Processors: An ILP Formulation

Today’s design methodologies for application-specific instruction-set processors (ASIPs) focus on the data-dominated domain characterized by computation-intensive applications such as digital signal processing. There is, however, a lack of methods for control-dominated domains such as network-protocol processing. These domains are characterized by branch-intensive applications with fine-grained timing constraints imposed by frequent interactions with the ASIP environment. The main challenge here is not to speed up over-all application runtime, but to meet the many timing constraints. This challenge can be addressed by introducing special instructions that speed up the timing-critical paths. In this paper we propose the first ASIP design methodology for the control-dominated domain. We divide the task into two separate optimization problems, each formulated as an integer linear program (ILP). The first is to find a complete set of operation sequences that must be implemented as macro instructions in order to meet given timing constraints. The second is to reduce the number of parallel instruction issues, achieved by bundling pairs of instructions. An ILP solver can automate the instruction-set synthesis, enabling the analysis of large benchmarks and yielding optimal solutions.

By: Gero Dittmann and Paul Hurley

Published in: RZ3611 in 2005


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