High-Density 3D Interconnect: Merging VLSI-CMOS and VLSI-MEMS Technologies

We have developed robust, wafer-scale, 3D interconnect methods for batch fabrication of System on Chip (SOC) especially suitable for MEMS or VLSI-MEMS applications, and show the robustness of these new transfer methods. This is a major step toward a high-integration SOC system and opens new opportunities for VLSI-MEMS and its integration with microelectronics. It has significant potential for many applications such as heterogeneous device integration (mixed technology), 3D integration and chip stacking. Using the third dimension also has the potential to simplify device architecture and reduce the length and complexity of interconnects.

By: M. Despont, U. Drechsler, R. Yu, M. Geissler, E. Delamarche, H.B. Pogge and P. Vettiger

Published in: RZ3491 in 2003


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