High Performance Self Resetting Circuits with Enhanced Testability

        Self resetting CMOS (SRCMOS) circuits are described, with their particular design and test issues. A methodology for circuit level testing of SRCMOS logic (or any kind of pulsed logic) is described. The methodology features the ability to inhibit the resets, to force resets, and to convert the circuits to a pseudo-static mode of operation, with noise and glitch recovery.

By: Terry I. Chappell (Intel), Ruud A. Haring, Talal K. Jaber (IBM Microelectronics Div., Austin, TX), Ed Seewann (IBM Microelectronics Div., Austin, TX), Michael P. Beakes, Barbara A. Chappell (Intel) and Bruce M. Fleischer

Published in: RC20321 in 1996

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