Evaluating Design Tradeoffs in On-Chip Power Management for CMPs

The continual scaling of process technology has resulted in a larger number of transistors available on a single chip and has thus enabled the dawn of Chip Multiprocessors (CMPs), where multiple processor cores are placed on a single chip. Additionally, power consumption remains a concern due to the thermal and reliability issues that result from high power dissipations. Dynamic power management techniques employed in current processors are designed for individual processor cores. With the shift towards multi-core chips, it is necessary to augment such per-core techniques with a larger chip-level control.

In this paper, we first model such a centralized power management unit in a full-system simulation environment. We implement asynchronous interfaces where needed to allow the individual cores of the CMP to operate at different voltages/frequencies and we also introduce the ability to adjust the fetch bandwidth of each processor core. Our model accounts for the cost of transition between power modes, as well as the control sampling time granularity constraints. To show the utility of our model, we then explore the design-tradeoffs associated with CMP power management solutions. We show that global power management solutions outperform the solutions that locally manage power per-core without any global chip-wide control. We then show that global power management is most effective at relatively fine granularities that allow it to adapt to changing workload behavior quickly and thus conclude that on-chip hardware solutions for CMP power management are important for future CMP microprocessors.

By: Joseph Sharkey; Alper Buyuktosunoglu; Pradip Bose

Published in: RC24086 in 2006


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