JiffyTune: Circuit Optimization Using Time-Domain Sensitivities

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Automating the transistor and wire sizing process is an important step towards being able to rapidly design high-performance, custom circuits. The task is best approached by means of gradient-based nonlinear optimization algorithms. This paper presents a circuit optimization tool that automates the tuning task by means of such an approach. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and wire tuning, general choices of objective functions and constraints, and recovery from non-working circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods we use a technique, called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms, the environment in which they are used and presents extensive results to corroborate the authors' enthusiasm for their application. This includes a circuit with 6,900 transistors that was optimized in about 108 minutes of CPU time on an IBM Risc/System 6000, model 590.

By: Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandu Visweswariah and Chai Wah Wu

Published in: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, volume 17, (no 12), pages in 1998

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