Video Coding for Decoding Power Constrained Embedded Devices

Copyright 2004 Society of Photo-Optical Instrumentation Engineers. This paper was (will be) published in and is made available as an electronic reprint [preprint] with permission of SPIE. Single print or electronic copies for personal use only are allowed. Systematic or multiple reproduction, distribution to multiple locations through an electronic listserver or other electronic means, duplication of any material in this paper for a fee or for commericial purposes, or modification of the content of the pater are all prohibited. By choosing to view or print this document, you agree to all the provisions of the copyright law protecting it.

Low power dissipation and fast processing time are crucial requirements for embedded multimedia devices. This paper presents a technique in video coding to decrease the power consumption at a standard video decoder. Coupled with a small dedicated video internal memory cache on a decoder, the technique can substantially decrease the amount of data traffic to the external memory at the decoder. A decrease in data traffic to the external memory at decoder will result in multiple benefits: faster real-time processing and power savings. The encoder, given prior knowledge of the decoder’s dedicated video internal memory cache management scheme, regulates its choice of motion compensated predictors to reduce the decoder’s external memory accesses. This technique can be used in any standard or proprietary encoder scheme to generate a compliant output bit stream decodable by standard CPU-based and dedicated hardware-based decoders for power savings with the best quality-power cost trade off. Our simulation results show that with a relatively small amount of dedicated video internal memory cache, the technique may decrease the traffic between CPU and external memory over 50%.

By: Ligang Lu, Vadim Scheinin

Published in: SPIE Proceedings, volume 5308, (no ), pages 37-44 in 2004


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