Accuracy and Speed-Up of Parallel Trace-Driven Architectural Simulation

Trace-driven simulation continues to be one of the main evaluation methods in the design of high performance processor-memory sub-systems. In view of the ever-increasing sizes of applications and thier dynamic traces, speed-up of existing simulation methods without significant loss of accuracy is important. In this paper, we examine the varying speed-up opportunities available by processing a given trace in parallel on IBM SP-2 machine. We consider three architectural analysis tools: a basic trace-analysis program, a multi-configuration cache simulator and a detailed cycle-by-cycle super scalar processor simulator (timer). Before designing our experimental strategy, we theorize on speed-up opportunites within the framework of available parallel programming alternatives on the SP-2, with the traces stored on a shared filesystem. We also develop a simple, yet effective method of correcting for cold-start cache miss errors, by use of overlapped trace chunks. We then report selected experimental results to validate our expectations. We show that through simple methods of combining per-node simulation statistics, coupled with overlapped trace chunks (where needed), it is possible to achieve near-perfect speed-up without loss of accuracy. Next, in order to achieve further reduction in simulation cost, we combine uniform sampling methods with parallel trace processing with a slight loss of accuracy for finite-cache timer runs. We then show that by using warm-start sequences from preceding trace chunks, it is possible to reduce the errors back to acceptable bounds...

By: A. T. Nguyen (Univ. of IL at Urbana), M. Michael (Univ. of Rochester), A. Nanda, K. Ekanadham, P. Bose

Published in: IEEE International Parallel Processing Symposium Proceedings. Los Alamitos, IEEE Computer Society Press. p. 39-44, IEEE in 1996

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