Architecture, compiler and simulation of a tree-based VLIW processor

        We describe a processor architecture based on very-long instruction
        word (VLIW) principles, its compiler, the evaluation
        approach used to measure its potential performance, and the
        simulation environment developed for experimenting and performing
        trade-offs analysis among alternative features of architecture
        and compiler.

        In this architecture, programs are encoded as sequences of
        tree-instructions which do not reflect the organization
        of the processor where they are executed. Tree-instructions are
        dynamically translated, during instruction cache reloading/accessing,
        into an implementation-specific VLIW form that preserves the simple
        instruction-dispatch logic characterizing VLIW processors. Large
        tree-instructions are dynamically pruned to fit into smaller
        implementations. This scheme makes possible object-code
        compatibility between VLIW processors with different organizations
        as well as with superscalar implementations, thus solving one of
        the most critical objections to the adoption of the VLIW paradigm
        in general-purpose architectures.

        The compiler uses state-of-the-art optimizing techniques to reach
        new levels of instruction-level parallelism, while also exhibiting
        much flexibility so that architecture/compiler/implementation
        trade-offs can be explored in several dimensions. The simulation
        environment integrates a collection of innovative and known
        techniques to deliver fast turn-around time for preliminary
        performance estimates, so that architecture/compiler trade-offs
        can be analyzed over complete execution runs, as well as complete
        cycle-by-cycle tracing and timing information.

By: J. H. Moreno, M. Moudgill, K. Ebcioglu, E. Altman, B. Hall, I. R. Miranda, S. K. Chen, A. Polyak

Published in: RC20495 in 1996


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