An Overview of Pb-free, Flip-Chip Wafer Bumping Technologies

To meet the European Union Restriction of Hazardous Substances (RoHS) requirements and the continuing demand for lower costs, finer pitch and high reliability flip chip packaging structures, considerable work is going on in electronic industry to develop Pb-free solutions for flip chip technology. In this paper, various solder bumping technologies developed for flip-chip applications are reviewed with an emphasis on a new wafer bumping technology called C4NP (Controlled-Collapse-Chip-Connect New Process). Several inherent advantages of C4NP technology are discussed over other technologies. This paper will also discuss the recent development and implementation of Pb-free C4 interconnections for 300 mm wafers demonstrated at IBM. In addition, some metallurgical issues associated with C4NP technology are discussed.

By: Sung K. Kang; Peter Gruber; Da-Yuan Shih

Published in: RC24582 in 2008


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