Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High Performance Digital Systems

        In this paper, a new high speed circuit technique: differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using the pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which will lead to eliminate the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit and it also provides superior performance with less power dissipation and better silicon area trade-off. The basic DCVSPG design technique, the methodlogy for optimization and synthesis of pass-gate are described. The standard cell library development by taking advantages of the dual-rail outputs of DCVSPG gates are also discussed. The performance comparisons with other existing pass-gate circuit techniques (CPS, DPL and SRPL) are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using DCVSPG circuit technique is demonstrated. The process that the design is based upon is 0.5 um CMOS technology with 0.25 um effective channel length and 5 layers of metal. This macro can run up to 500 MHz under the nominal process conditions. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance.

By: F. S. Lai and W. Hwang

Published in: RC20434 in 1996

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