Leakage and Leakage Sensitivity Computation for Combinational Circuits

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. It has been shown in many reports that leakage is increasing dramatically with each technology generation and is expected to dominate total system power. Motivated by the need for accurate estimation of the leakage power, this paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation on combinational circuits. A probabilistic technique is employed to compute the average leakage of combinational circuits under all possible input patterns. We also show that the input dependency of the leakage for large combi-national circuits is fairly small due to an averaging effect. The proposed technique gives very accurate results with an average error of only 2% for the ISCAS circuit benchmarks. We also extend the proposed technique to predict the leakage power components separately, by predicting the subthreshold and gate leakage components of the circuit. Furthermore, the leakage sensitivities of the circuit with respect to environmental and process variables can be also predicted by the proposed method. We demonstrate the application of predicted sensitivities in building practical compact models of leakage power. The leakage sensitivities can be employed in a wide range of applications including in optimizing the circuit performance, manufacturing yield and product quality.

By: Emrah Acar, Anirudh Devgan, Rahul Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns

Published in: RC22825 in 2003


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