3D Monolithic Integration of III-V and Si(Ge) FETs for hybrid CMOS and Beyond

3D Monolithic integration can enable higher density and has the potential to stack independently optimized
layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited
to be used as the top layer channel material in 3D monolithic integation along with Si/Si(Ge) FETs. A review
of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

By: V. Deshpande, V. Djara, E. O‘Connor, P. Hashemi, T. Morf, K. Balakrishnan, D.Caimi, M. Sousa, J. Fompeyrine and L. Czornomaz

Published in: Japanese Journal of Applied Physics, volume 56, (no 04CA05 ), pages 10.7567/JJAP.56.04CA05 in 2017


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