Vertical Interconnection Technology for 3D Integration

Semiconductor devises have continued to rapidly get smaller with higher integration in following Moore’s Law. As a result, performance including speed, functionality, and power consumption has improved while costs have also been reduced. However, as the size of these devises has also decreased (such as 90nm and 65nm), which causes management issues such as increased investment and increased research and development costs, and has also caused technical issues such as increased transistor leakage current. Therefore, it has become more difficult to minimize the size at the same pace as the speed. It is believed that the development of the three dimensional System-in-Package (SiP), which combines multiple LSIs three dimensionally, is an effective solution to these issues.
In the conventional 3D lamination method for LSIs, through silicon vias are created in the silicon, insulation layer is deposited inside of the vias, and a conductive material is deposited using electroplating or a Chemical Vapor Deposition (CVD) to create vertical interconnection wiring. However, this method includes technically difficult processes. For example, metal needs to be deposited in the through-holes with a high aspect ratio. This process also takes much time. It takes time to do alignment, heating and pressure bonding when stacking multiple LSI layers each time. As a result, total throughput of fabricating 3D chip stack is low.

By: Katsuyuki Sakuma

Published in: RT5314 in 2010


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JP820080361_vertical interconnect_research report.pdf

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