QPX Architecture: Quad Processing eXtension to the Power ISA(TM)

This document defines the Blue Gene/Q Quad-Processing eXtension (QPX) to IBM’s Power Instruction Set Architecture. Refer to IBM’s Power ISATM AS architecture document for descriptions of the base Power instruction set, the storage model, and related facilities available to the application programmer.

The computational model of the QPX architecture is a vector Single Instruction Multiple Data (SIMD) model with four execution slots and a register file containing 32 registers of 256 bits. Each of the 32 registers can be envisioned as containing four elements of 64 bits, whereby each of the execution slots operates on one vector element.

By: Thomas Fox, Michael Gschwind, Jaime Moreno

Published in: RC25291 in 2012


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