HotSpot 6.0: Validation, Acceleration and Extension

The challenge of removing the heat generated by microprocessors with reasonable cost has long been identified as a critical issue [9]. As a matter of fact, the cooling constraint (a.k.a., thermal wall) has became a major hurdle that limits the scaling of operating frequency and transistor density. As a fast and accurate thermal model, HotSpot [1] enables early-stage evaluation of chip temperature and therefore supports architectural study of dynamic thermal management strategies, chip floorplanning, and novel cooling solutions.

The recent industry trend of moving toward tighter in-package integration (e.g., stacked DRAM) brings both opportunities and challenges. From a thermal design point of view, such integration along the third dimension significantly increases the density of heat emission and therefore requires more efficient cooling solutions as well as thermal management techniques. From a thermal modeling perspective, 3D integration raises the complexity of the problem in terms of both problem size and system heterogeneity. In order to further facilitate thermal modeling for 3D integrated silicon chips, we developed a new version of HotSpot (version 6.0) with the following new features:

    • Calibration/validation against representative reference data created under mentorship from an experienced IBM POWER-family power/thermal modeling team.
    • Improved steady-state solver.
    • Support layers with non-uniform thermal resistivity and heat capacity. This feature is originally contributed by Prof. Ayse Coskun’s group in Boston University.
    • Improved support for secondary heat transfer path.

HotSpot version 6.0 is available at This report provides a detailed description for all the major new features.

By: Runjie Zhang, Mircea R. Stan, Kevin Skadron

Published in: RC25545 in 2015


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