Ground Bounce and Ground Bounce Reduction Techniques of Power Gate Structure

In this paper, we address ground bounce caused by discharge current through a sleep transistor when making a power mode transition in a power gated CMOS circuit. Several ground bounce reduction techniques are proposed to reduce the magnitude of voltage glitches on the power and ground rails as well as methods to reduce the time required to stabilize power and ground. To evaluate our ground bounce reduction techniques in 0.13 um CMOS technology, we implemented arithmetic and logic units (ALUs) with a maximum frequency of 500MHz at 1.5V and simulated them with PowerSpice fixtured in a package model. The experimental simulation results demonstrate the effectiveness of the ground bounce reduction techniques.

By: Suhwan Kim, Stephen Kosonocky, D. R. Knebel

Published in: RC22694 in 2003


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