Co-Integration of III-V with Si for Scaled CMOS

Relentless scaling of CMOS transistors has continued despite formidable challenges in lithography and processing. However, scaling to sub-20-nm dimensions presents unique challenges that threaten to end Moore’s scaling within the next decade (Table 1).

By: Devendra K. Sadana

Published in: RC25299 in 2012


Questions about this service can be mailed to .