Register Constraint Back-propagation Working in Collaboration with a Register Manager

Machine instruction specifications and register usage conventions may drastically constrain symmetric register allocation. This often causes a large decrease of the quality in generated code, because the compiler has to generate additional instructions to meet specifications or conventions. The performance decrease is very conspicuous, especially for small-register-set architectures such as that of the Intel X86 series. Enhanced graph coloring including register coalescing can solve this problem, but in the environment of a just-in-time compilation, register allocation by graph coloring is so costly that many of such compilers adopt other register allocation techniques like linear scan. This kind of on-the-fly register allocator is often called the register manager, in which the problem becomes worse due to the lack of information on interference among live ranges of local variables. This paper describes a method for enhancing the quality of generated code by using data-flow to propagate the register constraint information to the intermediate code while taking account of interference among local variables. We implemented this method on the just-in-time compiler for IBM Developer Kit for Windows, version 1.1.8. The experimental results show that the method yields a performance increase of up to 10 percent in SPEC JVM98, CaffeineMark 3.0 and JMark 2.0

By: Akira Koseki and Hideaki Komatsu

Published in: RT0551 in 2007

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