A Tutorial Example of a Cache Memory Protocol and RTL Implementation

This technical report is intended to facilitate research on the problem of showing that a hardware implementation is a correct implementation of a higher level model. We provide a tutorial example of a cache memory protocol and an implementation of the protocol in VHDL. Cache memory protocols are an important subject for formal verification, because these protocols are notoriously difficult to design and implement correctly. Although there is a considerable body of theory about verifying that an implementation is correct with respect to a high level model, such verifications are rare in industry. By providing realistic examples of both a high level model and its implementation, we hope to encourage the development of practical verification methods that can be used in industry.

By: Steven M. German; Geert Janssen

Published in: RC23958 in 2006


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