High Performance Viterbi Decoder on Cell/B.E.

Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA, or optimized hardware accelerators. With the rapid development of the multicore technology, the multicore platforms become a reasonable choice for the software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core platform designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one SPE running at 3.2GHz, the viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on CELL platform

By: Junjie Lai; Jianwen Chen

Published in: RC24644 in 2008


This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.


Questions about this service can be mailed to reports@us.ibm.com .