The assessment of on-chip wire-length distribution models

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This paper presents a comparison of wirelength distributions and interconnection count obtained with existing wirelength distribution models with on-chip wirelength distributions and actual number of interconnections in ASIC-like designs of a high-performance microprocessor. The actual distributions and number of interconnections are obtained from measurements of 100 control logic
designs in the IBM POWER4 chip. In order to obtain wirelength distributions and estimates of number of interconnections with existing models, two empirical parameters are first extracted from the actual design data with the use of Rent's Rule. These two parameters are used as inputs in the existing models. Lack of agreement between the data and models is observed, and possible reasons for the lack of agreement are discussed and proposed as future work to improve existing models and to improve wirelength estimates.

By: Mary Yvonne Wisniewski, Giovanni Fiorenza, Rick A. Rand

Published in: IEEE Transactions on Very Large Scale Integration Systems, volume 12, (no 10), pages 1108-12 in 2004


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